1. Field of the Invention
The present invention relates to a buffer circuit and more specifically to a buffer circuit that can improve a slew rate characteristic under a low current consumption.
2. Description of the Related Art
In recent years, in an output buffer circuit used in various driver ICs and the like, a buffer circuit for satisfying characteristics in a trade-off relationship to each other, such as a large capacity driving power, a lower power consumption, and a high-speed output response has been needed.
As a conventional buffer circuit for outputting an input voltage, which is input into an input terminal, from an output terminal as an output voltage, a diamond-shaped buffer circuit, which is disclosed in Japanese Patent Application Laid-Open No. 2002-185269, has been known.
The above buffer circuit is formed by combination of source follower circuits of an output NMOS (N-channel MOS field-effect transistor) and a PMOS (P-channel MOS field-effect transistor). The diamond-shaped buffer circuit is a circuit that can operate at a high-speed with a low current consumption and simple circuitry.
As a buffer circuit for outputting a voltage signal to an output terminal by charging and discharging electricity for a load capacity connected with the output terminal according to a voltage signal input into an input terminal, a type of a buffer circuit using a differential amplifier has been known.
The above buffer circuit operates as it applies the voltage signal to a non-inverting input terminal of the differential amplifier, in which an inverting input terminal and the output terminal are directly connected with each other, and outputs the voltage signal from the output terminal of the differential amplifier to the output terminal.
As a buffer circuit that can operate at a high-speed with a low current consumption and simple circuitry, the diamond-shaped buffer circuit is advantageous.
If the above mentioned diamond-shaped buffer circuit has a big load capacity connected with the output terminal, the areas of the elements of an output NMOS and an output PMOS, which form an output part, need to be increased. If the areas are increased, gate terminal capacities of the output NMOS and the output PMOS are also increased.
Therefore, if current for driving the gate terminal capacity is small, the gate terminal voltage of the output NMOS and the gate terminal voltage of the output PMOS can neither charge nor discharge according to abrupt variation of the input voltage to the input terminal. That delays response, and accordingly, the response of the output voltage from the output terminal is delayed.
In order to make the output voltage from the output terminal respond rapidly to the input voltage to the input terminal, the current for driving the gate terminal capacities of the output NMOS and the output PMOS, which form the output part, needs to be increased. As the current steadily flows, however, it impedes lowering the consumption of the electricity.
As the lower power consumption and the high-speed output response are in trade-off relationship as mentioned above, it has been difficult to realize the buffer circuit that satisfies both of the characteristics.